Custom Query (1030 matches)

Running the simple test case from ticket:717 results in a trip to the kernel debugger with the complaint:

unexpected instruction preceding alloc trap.

The unexpected instruction is the (relatively new) branch around an unconditional uuo_alloc_trap. If pc_luser_xp() notes that a thread is at the alloc_trap, it expects the immediately preceding instruction to be a comparison, and that's now an instruction earlier.

This function is derived from cmucl-type-prop.13 from the test suite. The ARM compiler appears to mis-compile it.

Welcome to Clozure Common Lisp Version 1.7-dev-r14779  (LinuxARM32)!
? (defun junk (p1)
  (declare (optimize (speed 2) (safety 2) (debug 1) (space 3))
	   (type (eql 64848.973) p1))
  (- (the (eql 64848.973f0) p1) -2808/1031))
JUNK
? (junk 64848.973)
> Error: value 353705262 is not of the expected type MACPTR.
> While executing: FUNCALL-WITH-XP-STACK-FRAMES, in process listener(1).
> Type :POP to abort, :R for a list of available restarts.
> Type :? for other options.
1 > (disassemble 'junk)
;;; (defun junk (p1) (declare (optimize (speed 2) (safety 2) (debug 1) (space 3)) (type (eql 64848.973) 
  (cmp nargs (:$ 4))
  (beq L12)
  (uuo-error-wrong-nargs (:? ne))
L12
  (mov imm0 (:$ 19))
  (stmdb (:! sp) (imm0 vsp fn lr))
  (mov fn temp2)
  (str arg_z (:@! vsp (:$ -4)))         ;[24]
NIL
1 > 

gdb shows the following disassembly:

   0x54549594:	cmp	r2, #4
   0x54549598:	beq	0x545495a0
   0x5454959c:			; <UNDEFINED> instruction: 0x17f001f8
   0x545495a0:	mov	r0, #19
   0x545495a4:	push	{r0, r10, r11, lr}
   0x545495a8:	mov	r11, r9
   0x545495ac:	str	r4, [r10, #-4]!
   0x545495b0:	andeq	r0, r0, r0
   0x545495b4:	andeq	r0, r0, r9
   0x545495b8:	andeq	r0, r0, r10, lsr #10
   0x545495bc:	ldrbpl	r9, [r4], #-1428	; 0x594
   0x545495c0:	ldrbpl	r9, [r4], #-1430	; 0x596
   0x545495c4:	ldrbpl	r9, [r4], #-1613	; 0x64d
   0x545495c8:	strtpl	r12, [r12], #-1686	; 0x696
   0x545495cc:	andeq	r0, r0, #0
   0x545495d0:	andeq	r0, r0, r10, ror r8
   0x545495d4:	strtpl	sp, [r0], #-1829	; 0x725
   0x545495d8:	ldrbpl	r9, [r4], #-1534	; 0x5fe
   0x545495dc:	ldrbpl	r9, [r4], #-2198	; 0x896
   0x545495e0:	andeq	r0, r0, r0, lsl #1

The ARM fp unit generally offers at least 32 single-float registers (s0-s31) and at least 16 double-float registers (d0-d15); modern VFP implementations offer more than 16 doubles.

s0 and s1 occupy the same 64 bits in a 128-bit vector register as does d0, s2 and s3 conflict with d1, etc.

The compiler thinks that (for instance) s1 and d0 are disjoint and thus (at least in theory) might try to keep distinct live values in conflicting FPRs.