Index: /trunk/ccl/compiler/PPC/ppc2.lisp
===================================================================
--- /trunk/ccl/compiler/PPC/ppc2.lisp	(revision 5503)
+++ /trunk/ccl/compiler/PPC/ppc2.lisp	(revision 5504)
@@ -1315,5 +1315,5 @@
              (is-32-bit (member type-keyword (arch::target-32-bit-ivector-types arch)))
              (is-64-bit (member type-keyword (arch::target-64-bit-ivector-types arch)))
-             (is-signed (member type-keyword '(:signed-8-bit-vector :signed-16-bit-vector :signed-32-bit-vector :fixnum-vector)))
+             (is-signed (member type-keyword '(:signed-8-bit-vector :signed-16-bit-vector :signed-32-bit-vector :signed-64-bit-vector :fixnum-vector)))
              (vreg-class (hard-regspec-class vreg))
              (vreg-mode
@@ -1675,5 +1675,5 @@
          (is-32-bit (member type-keyword (arch::target-32-bit-ivector-types arch)))
          (is-64-bit (member type-keyword (arch::target-64-bit-ivector-types arch)))
-         (is-signed (member type-keyword '(:signed-8-bit-vector :signed-16-bit-vector :signed-32-bit-vector :fixnum-vector)))
+         (is-signed (member type-keyword '(:signed-8-bit-vector :signed-16-bit-vector :signed-32-bit-vector :signed-64-bit-vector :fixnum-vector)))
          (vreg-class (if vreg (hard-regspec-class vreg)))
          (vreg-mode (if (or (eql vreg-class hard-reg-class-gpr)
@@ -1772,5 +1772,5 @@
            (is-32-bit (member type-keyword (arch::target-32-bit-ivector-types arch)))
            (is-64-bit (member type-keyword (arch::target-64-bit-ivector-types arch)))
-           (is-signed (member type-keyword '(:signed-8-bit-vector :signed-16-bit-vector :signed-32-bit-vector :fixnum-vector)))
+           (is-signed (member type-keyword '(:signed-8-bit-vector :signed-16-bit-vector :signed-32-bit-vector :signed-64-bit-vector :fixnum-vector)))
            (result-is-node-gpr (and (eql (hard-regspec-class result-reg)
                                          hard-reg-class-gpr)
@@ -1870,5 +1870,5 @@
            (is-32-bit (member type-keyword (arch::target-32-bit-ivector-types arch)))
            (is-64-bit (member type-keyword (arch::target-64-bit-ivector-types arch)))
-           (is-signed (member type-keyword '(:signed-8-bit-vector :signed-16-bit-vector :signed-32-bit-vector :fixnum-vector))))
+           (is-signed (member type-keyword '(:signed-8-bit-vector :signed-16-bit-vector :signed-32-bit-vector :signed-64-bit-vector :fixnum-vector))))
       (cond ((and is-node node-value-needs-memoization)
              (unless (and (eql (hard-regspec-value src) ppc::arg_x)
@@ -2008,28 +2008,28 @@
              (unscaled-idx ($ ppc::arg_y))
              (result-reg ($ ppc::arg_z)))
-      (cond (needs-memoization
-             (ppc2-three-targeted-reg-forms seg
-                                            vector src
-                                            index unscaled-idx
-                                            value result-reg))
-            (t
-             (setq result-reg (ppc2-target-reg-for-aset vreg type-keyword))
-             (ppc2-three-targeted-reg-forms seg
-                                            vector src
-                                            index unscaled-idx
-                                            value result-reg)))
-      (when safe
-        (let* ((*available-backend-imm-temps* *available-backend-imm-temps*)
-               (value (if (eql (hard-regspec-class result-reg)
-                               hard-reg-class-gpr)
-                        (hard-regspec-value result-reg))))
-          (when (and value (logbitp value *available-backend-imm-temps*))
-            (setq *available-backend-imm-temps* (bitclr value *available-backend-imm-temps*)))
-          (if (typep safe 'fixnum)
-            (! trap-unless-typecode= src safe))
-          (unless index-known-fixnum
-            (! trap-unless-fixnum unscaled-idx))
-          (! check-misc-bound unscaled-idx src)))
-      (ppc2-vset1 seg vreg xfer type-keyword src unscaled-idx index-known-fixnum result-reg (ppc2-unboxed-reg-for-aset seg type-keyword result-reg safe constval) constval needs-memoization)))))
+        (cond (needs-memoization
+               (ppc2-three-targeted-reg-forms seg
+                                              vector src
+                                              index unscaled-idx
+                                              value result-reg))
+              (t
+               (setq result-reg (ppc2-target-reg-for-aset vreg type-keyword))
+               (ppc2-three-targeted-reg-forms seg
+                                              vector src
+                                              index unscaled-idx
+                                              value result-reg)))
+        (when safe
+          (let* ((*available-backend-imm-temps* *available-backend-imm-temps*)
+                 (value (if (eql (hard-regspec-class result-reg)
+                                 hard-reg-class-gpr)
+                          (hard-regspec-value result-reg))))
+            (when (and value (logbitp value *available-backend-imm-temps*))
+              (setq *available-backend-imm-temps* (bitclr value *available-backend-imm-temps*)))
+            (if (typep safe 'fixnum)
+              (! trap-unless-typecode= src safe))
+            (unless index-known-fixnum
+              (! trap-unless-fixnum unscaled-idx))
+            (! check-misc-bound unscaled-idx src)))
+        (ppc2-vset1 seg vreg xfer type-keyword src unscaled-idx index-known-fixnum result-reg (ppc2-unboxed-reg-for-aset seg type-keyword result-reg safe constval) constval needs-memoization)))))