Index: /branches/rme-fpe/lisp-kernel/constants.h
===================================================================
--- /branches/rme-fpe/lisp-kernel/constants.h	(revision 13935)
+++ /branches/rme-fpe/lisp-kernel/constants.h	(revision 13936)
@@ -24,4 +24,5 @@
 #define TCR_FLAG_BIT_FOREIGN_EXCEPTION (fixnumshift+6)
 #define TCR_FLAG_BIT_PENDING_SUSPEND (fixnumshift+7)
+#define TCR_FLAG_BIT_FOREIGN_FPE (fixnumshift+8)
 
 #define TCR_STATE_FOREIGN (1)
Index: /branches/rme-fpe/lisp-kernel/x86-constants.h
===================================================================
--- /branches/rme-fpe/lisp-kernel/x86-constants.h	(revision 13935)
+++ /branches/rme-fpe/lisp-kernel/x86-constants.h	(revision 13936)
@@ -17,12 +17,49 @@
 #include "constants.h"
 
+/* MXCSR bits */
 
-/* FP exception mask bits */
-#define MXCSR_IM_BIT (7)        /* invalid masked when set*/
-#define MXCSR_DM_BIT (8)        /* denormals masked when set*
-#define MXCSR_ZM_BIT (9)        /* divide-by-zero masked when set */
-#define MXCSR_OM_BIT (10)       /* overflow masked when set */
-#define MXCSR_UM_BIT (11)       /* underflow masked when set */
-#define MXCSR_PM_BIT (12)       /* precision masked when set */
+enum {
+  MXCSR_IE_BIT,    /* invalid operation */
+  MXCSR_DE_BIT,	   /* denormal */
+  MXCSR_ZE_BIT,	   /* divide-by-zero */
+  MXCSR_OE_BIT,	   /* overflow */
+  MXCSR_UE_BIT,	   /* underflow */
+  MXCSR_PE_BIT,	   /* precision */
+  MXCSR_DAZ_BIT,   /* denorms-are-zero (not IEEE) */
+  MXCSR_IM_BIT,	   /* invalid operation masked */
+  MXCSR_DM_BIT,	   /* denormal masked */
+  MXCSR_ZM_BIT,	   /* divide-by-zero masked */
+  MXCSR_OM_BIT,	   /* overflow masked */
+  MXCSR_UM_BIT,	   /* underflow masked */
+  MXCSR_PM_BIT,	   /* precision masked */
+  MXCSR_RC0_BIT,   /* rounding control bit 0 */
+  MXCSR_RC1_BIT,   /* rounding control bit 1 */
+  MXCSR_FZ_BIT	   /* flush-to-zero (not IEEE) */
+};
+
+#define MXCSR_STATUS_MASK ((1 << MXCSR_IE_BIT) | \
+			   (1 << MXCSR_DE_BIT) | \
+			   (1 << MXCSR_ZE_BIT) | \
+			   (1 << MXCSR_OE_BIT) | \
+			   (1 << MXCSR_UE_BIT) | \
+			   (1 << MXCSR_PE_BIT))
+
+#define MXCSR_CONTROL_AND_ROUNDING_MASK ((1<<MXCSR_IM_BIT) | \
+                                         (1<<MXCSR_DM_BIT) | \
+                                         (1<<MXCSR_ZM_BIT) | \
+                                         (1<<MXCSR_OM_BIT) | \
+                                         (1<<MXCSR_UM_BIT) | \
+                                         (1<<MXCSR_PM_BIT) | \
+                                         (1<<MXCSR_RC0_BIT) | \
+                                         (1<<MXCSR_RC1_BIT))
+
+#define MXCSR_CONTROL_MASK ((1<<MXCSR_IM_BIT) | \
+                            (1<<MXCSR_DM_BIT) | \
+                            (1<<MXCSR_ZM_BIT) | \
+			    (1<<MXCSR_OM_BIT) | \
+			    (1<<MXCSR_UM_BIT) | \
+			    (1<<MXCSR_PM_BIT))
+
+#define MXCSR_WRITE_MASK (~((1<<MXCSR_DAZ_BIT)|(1<<MXCSR_FZ_BIT)))
 
 /* Bits in the xFLAGS register */