Changeset 13445


Ignore:
Timestamp:
Feb 10, 2010, 4:28:48 AM (10 years ago)
Author:
rme
Message:

x862-vset1: avoid stealing an extra immediate register on x8632 in the
32-bit case.

Also don't add in misc-data-offset when a known-fixnum index is
greater than max-xxx-bit-constant-index. (Large constant index values
are evidently quite rare...)

File:
1 edited

Legend:

Unmodified
Added
Removed
  • trunk/source/compiler/X86/x862.lisp

    r13443 r13445  
    24052405                   (! misc-set-node val-reg src unscaled-idx)))))
    24062406            (t
    2407              (with-additional-imm-reg (src unscaled-idx val-reg)
    2408                (with-imm-target (unboxed-val-reg) scaled-idx
    2409                  (cond
    2410                    (is-64-bit
    2411                     (if (and index-known-fixnum
    2412                              (<= index-known-fixnum
    2413                                  (arch::target-max-64-bit-constant-index arch)))
    2414                       (if (eq type-keyword :double-float-vector)
    2415                         (! misc-set-c-double-float unboxed-val-reg src index-known-fixnum)
    2416                         (if is-signed
    2417                           (! misc-set-c-s64 unboxed-val-reg src index-known-fixnum)
    2418                           (! misc-set-c-u64 unboxed-val-reg src index-known-fixnum)))
    2419                       (progn
     2407             (cond
     2408               (is-64-bit
     2409                (if (and index-known-fixnum
     2410                         (<= index-known-fixnum
     2411                             (arch::target-max-64-bit-constant-index arch)))
     2412                  (if (eq type-keyword :double-float-vector)
     2413                    (! misc-set-c-double-float unboxed-val-reg src index-known-fixnum)
     2414                    (if is-signed
     2415                      (! misc-set-c-s64 unboxed-val-reg src index-known-fixnum)
     2416                      (! misc-set-c-u64 unboxed-val-reg src index-known-fixnum)))
     2417                  (progn
     2418                    (if index-known-fixnum
     2419                      (x862-absolute-natural seg unscaled-idx nil (ash index-known-fixnum 3)))
     2420                    (if (eq type-keyword :double-float-vector)
     2421                      (! misc-set-double-float unboxed-val-reg src unscaled-idx)
     2422                      (if is-signed
     2423                        (! misc-set-s64 unboxed-val-reg src unscaled-idx)
     2424                        (! misc-set-u64 unboxed-val-reg src unscaled-idx))))))
     2425               (is-32-bit
     2426                (if (and index-known-fixnum
     2427                         (<= index-known-fixnum
     2428                             (arch::target-max-32-bit-constant-index arch)))
     2429                  (if (eq type-keyword :single-float-vector)
     2430                    (if (eq (hard-regspec-class unboxed-val-reg)
     2431                            hard-reg-class-fpr)
     2432                      (! misc-set-c-single-float unboxed-val-reg src index-known-fixnum)
     2433                      (! misc-set-c-u32 unboxed-val-reg src index-known-fixnum))
     2434                    (if is-signed
     2435                      (! misc-set-c-s32 unboxed-val-reg src index-known-fixnum)
     2436                      (! misc-set-c-u32 unboxed-val-reg src index-known-fixnum)))
     2437                  (progn
     2438                    (target-arch-case
     2439                     (:x8632
     2440                      (with-node-target (src) scaled-idx
    24202441                        (if index-known-fixnum
    2421                           (x862-absolute-natural seg unscaled-idx nil (+ (arch::target-misc-dfloat-offset arch) (ash index-known-fixnum 3))))
    2422                         (if (eq type-keyword :double-float-vector)
    2423                           (! misc-set-double-float unboxed-val-reg src unscaled-idx)
    2424                           (if is-signed
    2425                             (! misc-set-s64 unboxed-val-reg src unscaled-idx)
    2426                             (! misc-set-u64 unboxed-val-reg src unscaled-idx))))))
    2427                    (is-32-bit
    2428                     (if (and index-known-fixnum
    2429                              (<= index-known-fixnum
    2430                                  (arch::target-max-32-bit-constant-index arch)))
    2431                       (if (eq type-keyword :single-float-vector)
    2432                         (if (eq (hard-regspec-class unboxed-val-reg)
    2433                                 hard-reg-class-fpr)
    2434                           (! misc-set-c-single-float unboxed-val-reg src index-known-fixnum)
    2435                           (! misc-set-c-u32 unboxed-val-reg src index-known-fixnum))
    2436                         (if is-signed
    2437                           (! misc-set-c-s32 unboxed-val-reg src index-known-fixnum)
    2438                           (! misc-set-c-u32 unboxed-val-reg src index-known-fixnum)))
    2439                       (progn
    2440                         (if index-known-fixnum
    2441                           (x862-absolute-natural seg scaled-idx nil (+ (arch::target-misc-data-offset arch) (ash index-known-fixnum 2)))
     2442                          (x862-lri seg scaled-idx (ash index-known-fixnum 2))
    24422443                          (! scale-32bit-misc-index scaled-idx unscaled-idx))
    24432444                        (if (and (eq type-keyword :single-float-vector)
     
    24472448                          (if is-signed
    24482449                            (! misc-set-s32 unboxed-val-reg src scaled-idx)
    2449                             (! misc-set-u32 unboxed-val-reg src scaled-idx))))))
    2450                    (is-16-bit
     2450                            (! misc-set-u32 unboxed-val-reg src scaled-idx)))))
     2451                     (:x8664
     2452                      (with-imm-target (unboxed-val-reg) scaled-idx
     2453                        (if index-known-fixnum
     2454                          (x862-lri seg scaled-idx (ash index-known-fixnum 2))
     2455                          (! scale-32bit-misc-index scaled-idx unscaled-idx))
     2456                        (if (and (eq type-keyword :single-float-vector)
     2457                                 (eql (hard-regspec-class unboxed-val-reg)
     2458                                      hard-reg-class-fpr))
     2459                          (! misc-set-single-float unboxed-val-reg src scaled-idx)
     2460                          (if is-signed
     2461                            (! misc-set-s32 unboxed-val-reg src scaled-idx)
     2462                            (! misc-set-u32 unboxed-val-reg src scaled-idx)))))))))
     2463               (is-16-bit
     2464                (with-additional-imm-reg (src unscaled-idx val-reg)
     2465                  (with-imm-target (unboxed-val-reg) scaled-idx
    24512466                    (if (and index-known-fixnum
    24522467                             (<= index-known-fixnum
     
    24572472                      (progn
    24582473                        (if index-known-fixnum
    2459                           (x862-absolute-natural seg scaled-idx nil (+ (arch::target-misc-data-offset arch) (ash index-known-fixnum 1)))
     2474                          (x862-lri seg scaled-idx (ash index-known-fixnum 1))
    24602475                          (! scale-16bit-misc-index scaled-idx unscaled-idx))
    24612476                        (if is-signed
    24622477                          (! misc-set-s16 unboxed-val-reg src scaled-idx)
    2463                           (! misc-set-u16 unboxed-val-reg src scaled-idx)))))
    2464                    (is-8-bit
     2478                          (! misc-set-u16 unboxed-val-reg src scaled-idx)))))))
     2479               (is-8-bit
     2480                (with-additional-imm-reg (src unscaled-idx val-reg)
     2481                  (with-imm-target (unboxed-val-reg) scaled-idx
    24652482                    (if (and index-known-fixnum
    24662483                             (<= index-known-fixnum
     
    24682485                      (if is-signed
    24692486                        (! misc-set-c-s8 unboxed-val-reg src index-known-fixnum)
    2470                         (! misc-set-c-u8  unboxed-val-reg src index-known-fixnum))
     2487                        (! misc-set-c-u8 unboxed-val-reg src index-known-fixnum))
    24712488                      (progn
    24722489                        (if index-known-fixnum
    2473                           (x862-absolute-natural seg scaled-idx nil (+ (arch::target-misc-data-offset arch) index-known-fixnum))
     2490                          (x862-lri seg scaled-idx index-known-fixnum)
    24742491                          (! scale-8bit-misc-index scaled-idx unscaled-idx))
    24752492                        (if is-signed
    24762493                          (! misc-set-s8 unboxed-val-reg src scaled-idx)
    2477                           (! misc-set-u8 unboxed-val-reg src scaled-idx)))))
    2478                    (is-1-bit
    2479                     (if (and index-known-fixnum (<= index-known-fixnum (arch::target-max-1-bit-constant-index arch)))
     2494                          (! misc-set-u8 unboxed-val-reg src scaled-idx)))))))
     2495               (is-1-bit
     2496                (with-additional-imm-reg (src unscaled-idx val-reg)
     2497                  (with-imm-target (unboxed-val-reg) scaled-idx
     2498                    (if (and index-known-fixnum
     2499                             (<= index-known-fixnum (arch::target-max-1-bit-constant-index arch)))
    24802500                      (if constval
    24812501                        (if (zerop constval)
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