Changeset 10785

Sep 17, 2008, 9:16:12 PM (11 years ago)

Add a few words about x8632 register usage and tagging.

1 edited


  • trunk/source/doc/src/implementation.xml

    r9176 r10785  
    604604                </listitem>
    605605              </itemizedlist>
     606              <para>
     607                On 32-bit x86, the default register partitioning scheme
     608                involves:
     609              </para>
     610              <itemizedlist>
     611                <listitem>
     612                  <para>
     613                  A single "immediate" register.
     614                  </para>
     615                  <para>
     616                    The EAX register is given the symbolic name
     617                    "imm0".
     618                  </para>
     619                </listitem>
     620                <listitem>
     621                  <para>
     622                    There are two "dedicated" registers.
     623                  </para>
     624                  <para>
     625                    ESP and EBP have dedicated functionality dictated by the
     626                    hardware and calling conventions.
     627                  </para>
     628                </listitem>
     629                <listitem>
     630                  <para>
     631                    5 "node" registers.
     632                  </para>
     633                  <para>
     634                    The remaining registers, (EBX, ECX, EDX, ESI, EDI) normally
     635                    contain node values.  As on x86-64, string instructions
     636                    that implicity use ESI and EDI are not used.
     637                  </para>
     638                </listitem>
     639              </itemizedlist>
     640              <para>
     641                There are times when this default partitioning scheme is
     642                inadequate.  As mentioned in the x86-64 section, there are
     643                instructions like the extended-precision MUL and DIV which
     644                require the use of EAX and EDX.  We therefore need a way to
     645                change this partitioning at run-time.
     646              </para>
     647              <para>
     648                Two schemes are employed.  The first uses a mask in the TCR
     649                that contains a bit for each register.  If the bit is set,
     650                the register is interpreted by the GC as a node register; if it's
     651                clear, the register is treated as an immediate register.  The
     652                second scheme uses the direction flag in the EFLAGS register.
     653                If DF is set, EDX is treated as an immediate register.
     654                (We don't use the string instructions, so DF isn't otherwise
     655                used.)
     656              </para>
    607658          <para>On the PPC, the static register partitioning scheme
    804855                  fact that the PPC has multiple condition-code fields
    805856                  keeps that extra test from being prohibitively
    806                   expensive.</para>
     857                  expensive.  On IA-32, we can't afford to dedicate a tag to
     858                  NIL. NIL is therefore just a distinguished CONS
     859                  cell, and we have to explicitly check for a NIL argument
     860                  in CONSP/RPLACA/RPLACD.
     861                </para>
    807862              </listitem>
    808863              <listitem>
    857912                  information in the rest of the word.  (This is where the
    858913                  sometimes-limiting value of 2^24 for
    859                   ARRAY-TOTAL-SIZE-LIMIT on PPC32 platforms comes from.)
     914                  ARRAY-TOTAL-SIZE-LIMIT on 32-bit platforms comes from.)
    860915                  The low byte of the header&mdash;sometimes called the
    861916                  uvector's subtag&mdash;is itself tagged (which means
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