source: release/1.9/source/lisp-kernel/x86-constants.h @ 16083

Last change on this file since 16083 was 13952, checked in by rme, 9 years ago

New scheme for dealing with floating point exceptions on x86-64 systems.

Currently, we mask floating point execptions around all foreign function
calls. While this may not be a huge component of FF call overhead, it
makes sense to avoid doing this for what is presumably an exceptional
case.

We now leave floating point exceptions enabled, but the exception
handler in the lisp kernel is prepared to deal with them: it saves
lisp's MXCSR, masks all floating point exceptions, and resumes
execution (after setting a flag in the TCR to note what it has done).
At the end of .SPffcall, we check this flag. If it is set, we
save the fp exception status, and restore lisp's original MXCSR.

  • Property svn:eol-style set to native
  • Property svn:keywords set to Author Date Id Revision
File size: 2.6 KB
Line 
1/*
2   Copyright (C) 2005-2009 Clozure Associates
3   This file is part of Clozure CL. 
4
5   Clozure CL is licensed under the terms of the Lisp Lesser GNU Public
6   License , known as the LLGPL and distributed with Clozure CL as the
7   file "LICENSE".  The LLGPL consists of a preamble and the LGPL,
8   which is distributed with Clozure CL as the file "LGPL".  Where these
9   conflict, the preamble takes precedence. 
10
11   Clozure CL is referenced in the preamble as the "LIBRARY."
12
13   The LLGPL is also available online at
14   http://opensource.franz.com/preamble.html
15*/
16
17#include "constants.h"
18
19/* MXCSR bits */
20
21enum {
22  MXCSR_IE_BIT,    /* invalid operation */
23  MXCSR_DE_BIT,    /* denormal */
24  MXCSR_ZE_BIT,    /* divide-by-zero */
25  MXCSR_OE_BIT,    /* overflow */
26  MXCSR_UE_BIT,    /* underflow */
27  MXCSR_PE_BIT,    /* precision */
28  MXCSR_DAZ_BIT,   /* denorms-are-zero (not IEEE) */
29  MXCSR_IM_BIT,    /* invalid operation masked */
30  MXCSR_DM_BIT,    /* denormal masked */
31  MXCSR_ZM_BIT,    /* divide-by-zero masked */
32  MXCSR_OM_BIT,    /* overflow masked */
33  MXCSR_UM_BIT,    /* underflow masked */
34  MXCSR_PM_BIT,    /* precision masked */
35  MXCSR_RC0_BIT,   /* rounding control bit 0 */
36  MXCSR_RC1_BIT,   /* rounding control bit 1 */
37  MXCSR_FZ_BIT     /* flush-to-zero (not IEEE) */
38};
39
40#define MXCSR_STATUS_MASK ((1 << MXCSR_IE_BIT) | \
41                           (1 << MXCSR_DE_BIT) | \
42                           (1 << MXCSR_ZE_BIT) | \
43                           (1 << MXCSR_OE_BIT) | \
44                           (1 << MXCSR_UE_BIT) | \
45                           (1 << MXCSR_PE_BIT))
46
47#define MXCSR_CONTROL_AND_ROUNDING_MASK ((1<<MXCSR_IM_BIT) | \
48                                         (1<<MXCSR_DM_BIT) | \
49                                         (1<<MXCSR_ZM_BIT) | \
50                                         (1<<MXCSR_OM_BIT) | \
51                                         (1<<MXCSR_UM_BIT) | \
52                                         (1<<MXCSR_PM_BIT) | \
53                                         (1<<MXCSR_RC0_BIT) | \
54                                         (1<<MXCSR_RC1_BIT))
55
56#define MXCSR_CONTROL_MASK ((1<<MXCSR_IM_BIT) | \
57                            (1<<MXCSR_DM_BIT) | \
58                            (1<<MXCSR_ZM_BIT) | \
59                            (1<<MXCSR_OM_BIT) | \
60                            (1<<MXCSR_UM_BIT) | \
61                            (1<<MXCSR_PM_BIT))
62
63#define MXCSR_WRITE_MASK (~((1<<MXCSR_DAZ_BIT)|(1<<MXCSR_FZ_BIT)))
64
65/* Bits in the xFLAGS register */
66#define X86_CARRY_FLAG_BIT (0)
67#define X86_PARITY_FLAG_BIT (2)
68#define X86_AUX_CARRY_FLAG_BIT (4)
69#define X86_ZERO_FLAG_BIT (6)
70#define X86_SIGN_FLAG_BIT (7)
71#define X86_DIRECTION_FLAG_BIT (10)
72#define X86_OVERFLOW_FLAG_BIT (11)
73
74#define STATIC_BASE_ADDRESS 0x00012000
75
76
77
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