Version 1 (modified by rme, 9 years ago) (diff)


A port of OpenMCL to IA-32 (Intel's name for the 32 bit x86 architecture) would be a win for several reasons.

The most obvious reason would be to support Apple hardware that isn't 64-bit capable. This includes the first-generation iMac, MacBook?, MacBook? Pro, and all Intel-based Mac Minis.

Another Mac OS X specific reason would be to support access to Cocoa and Carbon on systems running Mac OS X Tiger, and to Carbon on Leopard. (Apple has publically confirmed that Carbon won't be 64 bit in Leopard.)

It would be interesting to support the AMD Geode LX (as used in the OLPC project) as the minimum processor. This processor supports the P6 family instructions, including MMX instructions. We can therefore use the conditional move instructions, and maybe some MMX instructions to help out with bignums.

On the other hand, the AMD Geode LX processor doesn't support any of the SSE/SSE2/SSE3 instructions; this means that we'd have to use the x87 FPU. This would require modifications to the compiler, which believes that every floating point register can be accessed independently.

It might be reasonable to target the Core Solo/Duo? processor, at least to begin with. This would cover all Intel-based Macintosh systems ever shipped, and would allow us to avoid adding x87 FPU support for now.

On Darwin, there will likely be a limit of 8K threads. This is because we will have to use i386_set_ldt to install a segment descriptor for each thread into the LDT, and the LDT can have only 8K entries. (While a thread is running, its segment descriptor is loaded into %fs, which is then used to point to thread-local storage. Some other operating systems provide nicer mechanisms for thread-local storage, such as the thread storage class.) The i386_set_ldt system call became available in Mac OS X 10.4.4.

We want to keep the precise GC. A strictly static register partitioning scheme is almost certainly not going to be sufficient. We should be able to use a bitmask in thread-local storage to indicate whether a register contains a node or an immediate value. The GC can then consult this mask when marking roots.

The tagging scheme would basically follows the PPC32 port. An important difference is that the three-bit tag #b101, which is for NIL on PPC32, would be used for tagged return addresses on IA-32.